View T81L0006A06_4122528.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tm
MCU
! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
TE CH
T81L0006A/B 8-bit A/D Type MCU 3. General Description
The T81L0006A/B is 8-bit microcontroller designed and developed with low power and high speed CMOS technology. It contains a 8K bytes OTP ROM, a 128 x 8 RAM, an 8-channels 8-bit A/D converter, 15/19 I/O lines, a watchdog timer, two 16-bit counter/timers, a seven source, two-priority level nested interrupt structure, two channel pulsed-width modulator (PWM), a full duplex UART, and an on-chip oscillator and clock circuits. In addition, the T81L0006A/B has two selectable modes of power reduction-idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
1. Features
Compatible with MCS-51 Embedded 8K Bytes OTP ROM 128 x 8-bit Internal RAM 15/19 Programmable I/O Lines for 20/24-pin Package Two 16-bit Timer/Counter & One 16-bit Timer Two External Interrupt Input (Only One Input for 20-pin Package) Two Channel PWM (Only One Channel PWM for 20-pin Package) Driving Capability up to 40 mA Embedded 1k bits EEPROM (for T81L0006B only) Programmable Serial UART Interface Low Power Idle & Power-down Modes Watch-dog Timer On-chip Crystal & RC Oscillator (Selected by Bonding Option) Internal Power-on Reset and External Reset Supported 8-Channel 8-bit A/D Converter SOP20/DIP20 & SOP24/DIP24 Package 3.3V Operating Voltage EEPORM Interface Low Voltage Reset
4. Order information
Part number T81L0006A-AK T81L0006A-BK T81L0006A-CK T81L0006A-DK T81L0006A-AD T81L0006A-BD T81L0006A-CD T81L0006A-DD T81L0006B-AK T81L0006B-BK T81L0006B-AD T81L0006B-BD Oscillator type RC Crystal RC Crystal RC Crystal RC Crystal RC Crystal RC Crystal EEPROM NONE NONE NONE NONE NONE NONE NONE NONE Embedded Embedded Embedded Embedded Package 24-pin DIP 24-pin DIP 20-pin DIP 20-pin DIP 24-pin SOP 24-pin SOP 20-pin SOP 20-pin SOP 24-pin DIP 24-pin DIP 24-pin SOP 24-pin SOP
!
2. Applications
*Meter *Household Appliances Controller *Handwriting Board *Charger *Sport Devices *Other Controller (Automotive, Toy...)
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 1
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
5. Block Diagram
RAM Addr. Register
RAM
OTP ROM
EEPROM
EEPROM interface
B Register
ACC
Stack Pointer Program Address Register
TMP2 W DT
TMP1
Buffer ALU PC Incrementer
Interrupt, Serial port, and Timer Block
PSW
Program Counter DPTR
RST
Timing & Control
Instruction Register
Port 3 Latch
PW M
Port 2 Latch
ADC
Port 1 Latch
OSC
Port 3 Drivers
Port 2 Drivers
Port 1 Drivers
XTAL1 XTAL2
P3.0 -P3.7
P2.0 P2.1 P2.3
P1.0 -P1.7
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 2
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
6. Pin Configuration
(RXD) P3.0 (TXD) P3.1 (ADI0) P1.0 (ADI1) P1.1 (INT1) P3.3 GND P2.3 (ADI2) P1.2 (ADI3) P1.3 (ADI4) P1.4 (ADI5) P1.5 (ADI6) P1.6 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 (T1) P3.5 (T0) P3.4 OSC-R STOP RST/VPP VCC P2.1 (VREF) P3.7 (PWM2) P2.0 (PWM1) P3.6 (INT0) P3.2 (ADI7) P1.7 (RXD) P3.0 (TXD) P3.1 (ADI0) P1.0 (ADI1) P1.1 (INT1) P3.3 GND P2.3 (ADI2) P1.2 (ADI3) P1.3 (ADI4) P1.4 (ADI5) P1.5 (ADI6) P1.6 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 (T1) P3.5 (T0) P3.4 XIN XOUT RST/VPP VCC P2.1 (VREF) P3.7 (PWM2) P2.0 (PWM1) P3.6 (INT0) P3.2 (ADI7) P1.7
DIP-24/SOP-24 For RC Oscillator T81L0006A-AK/ T81L0006A-AD T81L0006B-AK/ T81L0006B-AD
DIP-24/SOP-24 For Crystal Oscillator T81L0006A-BK/ T81L0006A-BD T81L0006B-BK/ T81L0006B-BD
(R XD) P3.0 (TXD) P3.1 (ADI0) P1.0 (ADI1) P1.1 GND (ADI2) P1.2 (ADI3) P1.3 (ADI4) P1.4 (ADI5) P1.5 (ADI6) P1.6
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
(T1) P3.5 (T0) P3.4 OSC -R STOP RST/VPP VCC (VR EF) P3.7 (PW M 1) P3.6 (INT0) P3.2 (ADI7) P1.7
(R XD) P3.0 (TXD) P3.1 (ADI0) P1.0 (ADI1) P1.1 GND (ADI2) P1.2 (ADI3) P1.3 (ADI4) P1.4 (ADI5) P1.5 (ADI6) P1.6
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
(T1) P3.5 (T0) P3.4 XIN XOUT RST/VPP VCC (VR EF) P3.7 (PW M 1) P3.6 (INT0) P3.2 (ADI7) P1.7
DIP-20/SOP-20 For RC Oscillator T81L0006A-CK/ T81L0006A-CD
DIP-20/SOP-20 For Crystal Oscillator T81L0006A-DK/ T81L0006A-DD
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 3
Publication Date: JAN. 2006 Revsion : C
tm
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TE CH
T81L0006A/B
7. Pin Description
Number Number (24-Pin) (20-Pin) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name P3.0/(RXD) P3.1/(TXD) P1.0/(ADI0) P1.1/(ADI1) P3.3/(INT1) GND P2.3 P1.2/(ADI2) P1.3/(ADI3) P1.4/(ADI4) P1.5/(ADI5) P1.6/(ADI6) P1.7/(ADI7) P3.2/(INT0) P3.6/(PWM1) P2.0/(PWM2) P3.7/(VREF) P2.1 VCC RST/VPP XOUT/(STOP) XIN/(OSC-R) P3.4/(T0) P3.5/(T1) I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type I/O I/O I/O I/O I/O Description General-purpose I/O pin (Default) or Serial input port. General-purpose I/O pin (Default) or Serial output port. General-purpose I/O pin (Default) or ADC input channel 0. General-purpose I/O pin (Default) or ADC input channel 1. General-purpose I/O pin (Default) or External interrupt source 1. Ground General-purpose I/O pin. General-purpose I/O pin (Default) or ADC input channel 2. General-purpose I/O pin (Default) or ADC input channel 3. General-purpose I/O pin (Default) or ADC input channel 4. General-purpose I/O pin (Default) or ADC input channel 5. General-purpose I/O pin (Default) or ADC input channel 6. General-purpose I/O pin (Default) or ADC input channel 7. General-purpose I/O pin (Default) or External interrupt source 0. General-purpose I/O pin (Default) or PWM signal output channel 1. General-purpose I/O pin (Default) or PWM signal output channel 2. General-purpose I/O pin (Default) or External reference voltage input pin for ADC. General-purpose I/O pin. 3.3V power supply. Reset signal input or programming supply voltage input. Crystal oscillator output terminal or stop RC oscillator network. Crystal oscillator input terminal or RC oscillator external resister connect pin. General-purpose I/O pin (Default) or Timer 0 external input pin. General-purpose I/O pin (Default) or Timer 1 external input pin.
8. Temperature Limit Ratings
Parameter Operating temperature Range Storage Temperature Range Rating -40 to +85 -55 to +125 Units C C
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 4
Publication Date: JAN. 2006 Revsion : C
tm
Symbol VCC ICC IPD
TE CH
T81L0006A/B
9. Electrical Characteristics
D.C Characteristics
Parameter Conditions Operating Voltage 25C Operating Current No load, ADC disable Vcc=3.3V Power-Down Current No load, Vcc=3.3V Only ADC Enable, Others IADC No load Disable VADC ADC Input Voltage Range VREF VREF input voltage range Vout >=VVOH(MIN.) VIH Hi-Level input voltage Vout <=VVOL(MIN.) Vout >=VVOH(MIN.) VIL Low-Level input voltage Vout <=VVOL(MIN.) IOH=-7uA VCC=MIN. IOH=-45uA VOH Hi-Level Output voltage VI=VIH or IOH=-70uA VIL IOH=-12mA** IOH=-20mA** IOL=12mA VCC=MIN. VOL1 * Low-Level Output voltage VI=VIH or IOL=25mA VIL IOL=40mA IOL=4mA VCC=MIN. VOL2 ** Low-Level Output voltage VI=VIH or IOL=12mA VIL IOL=20mA Note : * for PWM pins (P3.6/PWM1 and P2.0/PWM2). ** for high driving current mode. Min 3.0 0 2 2.1 2.9 2.4 1.9 2.4 1.9 Typ 3.3 6 120 Max 3.6 1 VREF VCC 0.6 Units V mA uA uA V V V V
-
-
V
-
0.2 0.4 0.6 0.2 0.4 0.6
V
V
A.C Characteristics
Symbol FSYS1 FSYS2 FADC tACT tRES tPOS tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tAVIV tRLRH tWLWH tRLDV tLLDV tAVDV tLLWL tAVWL tWHLH Parameter System Clock 1 (Crystal OSC) System Clock 2 (RC OSC) ADC Clock Frequency ADC Conversion Time External Reset High Pulse Width Power ON Start up Time ALE pulse width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN pulse width PSEN Low to Valid Instruction In Address to Valid Instruction In RD pulse width WR pulse width RD Low to Valid data in ALE Low to Valid data in Address to Valid data in ALE Low to RD or WR Low Address to RD or WR Low RD or WR High to ALE High Conditions VCC=3.3V VCC=3.3V Min 127 43 48 43 205 400 400 200 203 43 Typ 12 12 125 128 10 20 Max 24 233 145 312 252 517 585 300 123 Units MHz MHz KHz us system cycle ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 5
Publication Date: JAN. 2006 Revsion : C
tm
1 2 3 4 5 6 7 8 9 10 11 12
TE CH
T81L0006A/B
10. Function Description
10.1 Reset
VCC
P30 P31 P10 P11 P33 VSS P23 P12 P13 P14 P15 P16
P35 P34 XIN XOUT RST VCC P21 P37 P20 P36 P32 P17
24 23 22 21 20 19 18 17 16 15 14 13
1 2 3 4 5 6 7 8 9 10 11 12
P30 P31 P10 P11 P33 VSS P23 P12 P13 P14 P15 P16
P35 P34 XIN XOUT RST VCC P21 P37 P20 P36 P32 P17
24 23 22 21 20 19 18 17 16 15 14 13
8.2K
T81L0006A/B T81L0006A/B
For Power on Reset only
For Power on Reset and External Reset
10.2 Oscillation
1 2 3 4 5 6 7 8 9 10 11 12 P30 P31 P10 P11 P33 VSS P23 P12 P13 P14 P15 P16 P35 P34 OSCR STOP RST VCC P21 P37 P20 P36 P32 P17 24 23 22 21 20 19 18 17 16 15 14 13 51K 1 2 3 4 5 6 7 8 9 10 11 12 P30 P31 P10 P11 P33 VSS P23 P12 P13 P14 P15 P16 P35 P34 XIN XOUT RST VCC P21 P37 P20 P36 P32 P17 24 23 22 21 20 19 18 17 16 15 14 13 Y1 2.2M 22p
22p
T81L0006A/B-A
T81L0006A/B-B
RC Oscillator
Crystal Oscillator
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 6
Publication Date: JAN. 2006 Revsion : C
tm
F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H
TE CH
T81L0006A/B
10.3 Special Function Register
B ACC PSW T2CON IP P3 IE P2 SCON P1 TCON P0*
T2MOD RCAP2L RCAP2H
TL2
TH2
SBUF TMOD SP TL0 DPL TL1 DPH TH0 TH1 WDREL PCON
*Note: P0:Internal still keeping, but for pad dominate, no external pin assignment
Accumulator : ACC
ACC is the Accumulator register. The mnemonics for Accumulator-Specific instructions, however, refer to the Accumulator simply as A.
B Register : B
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.
Program Status Word : PSW
The PSW register contains program status information as detailed in CY AC F0 RS1 RS0 OV -P
BIT SYMBOL FUNCTION PSW.7 CY Carry flag. PSW.6 AC Auxiliary Carry flag. (For BCD operations.) PSW.5 F0 Flag 0. (Available to the user for general purposes.) PSW.4 RS1 Register bank select control bit 1. Set/cleared by software to determine working register bank. (See Note.) PSW.3 RS0 Register bank select control bit 0. Set/cleared by software to determine working register bank. (See Note.) PSW.2 OV Overflow flag. PSW.1 -- User-definable flag. PSW.0 P Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the Accumulator, i.e., even parity. NOTE: The contents of (RS1, RS0) enable the working register banks as follows: (0,0)-- Bank 0 (00H-07H) (0,1)-- Bank 1 (08H-0fH) (1,0)-- Bank 2 (10H-17H) (1,1)-- Bank 3 (18H-17H)
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 7
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
Stack Pointer : SP
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at locations 08H.
Data Pointer (DPTR) : DPH & DPL
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 1.0~1.7 & 2.0,2.1,2.3 & 3.0~3.7
All Ports are the SFR latches, respectively. Writing a one to a bit of a port SFR (P1 or P2 or P3) causes the corresponding port output pin to switch high. Writing a zero causes the port output pin to switch low. When used as an input, the external state of a port pin will be held in the port SFR (i.e., if the external state of a pin is low, the corresponding port SFR bit will contain a `0'; if it is high, the bit will contain a `1').
Serial Data Buffer : SBUF
The Serial Buffer is actually two separate registers, a transmit buffer and a receive buffer. When data is moved to SBUF, it goes to the transmit buffer and is held for serial transmission. (Moving a byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer.
Timer Registers : TH0, TL0, TH1, TL1,TH2,TL2
Register pairs (TH0, TL0) and (TH1, TL1) and (TH2, TL2) are 16-bit Counting registers for Timer/Counters 0 and Timer1and Timer2, respectively. .
Control Register : IP, IE, TMOD, TCON, SCON, PCON
Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port. They are described in later sections.
Standard Serial Interface
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = `0' and REN = `1'. Reception is initiated in the other modes by the incoming start bit if REN = `1'.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 8
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = `1'. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is `1' in an address byte and `0' in a data byte. With SM2 = `1', no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, in Mode 1 can be used to check the validity of the stop bit. In Mode 1 reception, if SM2 = `1', the receive interrupt will not active unless a valid stop bit is received.
Serial Port Control Register
The serial port control and status register is the Special Function Register SCON, shown in Figure 11. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
Baud Rates
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency / 12. The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = `0' (which is the value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = `1', the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate =2 SMOD/64* (Oscillator Frequency) In the T81L0006A/B, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. SCON MSB SM0
SM1
SM2
REN
TB8
RB8
TI
LSB RI
Where SM0, SM1 specify the serial port mode, as follows: SM0 SM1 Mode Description Baud Rate shift register f OSC / 12 0 0 0 8-bit UART Variable 0 1 1 9-bit UART UART FOSC /64 or FOSC /32 1 0 2 9-bit UART Variable 1 1 3 Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1, 3 Baud Rate =2 SMOD/32* (Timer 1 Overflow Rate) The Timer 1 interrupt should be disabled in this application. The Timer 1 itself can be configured for either "timer" or "counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate =2 SMOD*(Oscillator Frequency)/ 32/12 / [256 _ (TH1)] One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Using Timer 2 to Generate Baud Rates Timer2 is selected as the baudrate generator by setting TCLK and/or RCLK in T2CON register as followed. T2CON (address : C8h) MSB LSB
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
T2CON.7: TF2 Timer2 overflow flag set by timer2 overflow and must be cleared by software. TF2 will not be set when either RCLK=1 or TCLK=1. T2CON.6: EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. when timer2 interrupt is enabled, EXF2=1 will cause the CPU to vector to the timer2 interrupt routine. EXF2 must be cleared by software. T2CON.5: RCLK Receive clock flag. When set, cause the serial port to use timer2 overflow pulses for its receive clock in
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 9
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
mode 1 and 3. RCLK=0 causes timer1 overflow to be used for the receive clock T2CON.4: TCLK Transmit clock flag. When set, cause the serial port to use timer2 overflow pulses for its transmit clock in mode 1 and 3. TCLK=0 causes timer1 overflow to be used for the transmit clock T2CON.3: EXEN2 Timer2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if timer2 is not being used to clock the serial port. EXEN2=0 causes timer2 to ignore events at T2EX. T2CON.2: Start/stop control for timer2. A logic 1 starts the timer T2CON.1: Timer or counter select. (Timer 2) , 0 as internal timer T2CON.0: Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2=1. When cleared, auto reloads will occur either with timer2 overflow or negative transitions at T2EX when EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on timer2 overflow. Note then the baudrates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer2 into its baudrate generator mode. The baudrate generator mode is similar to the auto reload mode, in that a rollover is TH2 causes the Timer2 registers to be reload with the 16 bit value in registers RCAP2H and RCAP2L, which are preset by software given by the formula. Baudrate= (Timer2 overflow rate)/16 =(Oscillator Frequency) / (32*(65536-(RCAP2H,RCAP2L)))
Serial Interface Timing Diagram
S1.........S6 S1.........S6 S1.........S6 S1.........S6 S1.........S6 S1.........S6 S1.........S6 S1.........S6 S1.........S6 S1.........S6
ALE
Write to SBUF
Send
Shift RXD D0 D1 D2 D3 D4 D5 D6 D7
TXD
Write to SCON, Clear RI
RI
Receive
Shift D0 RXD D1 D2 D3 D4 D5 D6 D7
TXD
Serial Port Mode 0
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 10
Publication Date: JAN. 2006 Revsion : C
Receive
Transmit
tm
TX clock Send Data
TE CH
T81L0006A/B
Write to SBUF
Shift TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop B it
TI RX clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop B it
Shift
RI
Serial Port M ode 1
TX clock Write to SBUF
Send
Data
Shift Stop Bit TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8
TI RX clock Stop Bit RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8
Shift
RI
Serial Port Mode 2
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 11
Publication Date: JAN. 2006 Revsion : C
Receive
Transmit
Receive
Transmit
tm
TX clock Send Data
TE CH
T81L0006A/B
Write to SBUF
Shift Stop Bit TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8
TI RX clock Stop Bit RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8
Shift
RI
Serial Port Mode 3
Interrupt Enable Register : IE
MSB EA EA wdt ET2 ES ET1 EX1 ET0 EX0 wdt ET2 ES ET1 EX1 ET0 LSB EX0
IE.7 Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. IE.6 Watchdog timer refresh flag. IE.5 Enable or disable the Timer 2 overflow interrupt. IE.4 Enable or disable the serial port interrupt. IE.3 Enable or disable the Timer 1 overflow interrupt. IE.2 Enable or disable External Interrupt 1. (See NOTE) IE.1 Enable or disable the Timer 0 overflow interrupt. IE.0 Enable or disable External Interrupt 0.
NOTE: if A/D converter interrupts enabled, EX1 interrupt function will be replaced.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 12
Publication Date: JAN. 2006 Revsion : C
Receive
Transmit
tm
TE CH
T81L0006A/B
Watchdog Timer
The watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After an external reset the watchdog timer is disabled and all registers are set to zeros.
! Watchdog Timer structure
The watchdog consists of 16-bit counter wdt, reload register wdtrel, prescalers by 2 and by 16 and control logic. Where wdtl=00h while start up.
Figure
Watchdog block diagram
! Start procedure
There are one way to start the watchdog. A programmer can start the watchdog as refreshing procedure. Once the watchdog is started it cannot be stopped unless rst signal becomes active. When wdt registers enters the state 7FFCh, asynchronous wdts signal will become active. The signal wdts sets the bit 6 in ip0 register and requests reset state. The wdts is cleared either by rst signal or change of the state of the wdt timer. Procedure: load wdtrel value # set "wdt" # set "swdt" in 12 instruction cycles.
! Refreshing the watchdog timer
The watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. This requirement imposes obligation on the programmer to issue two followed instructions. The first instruction sets wdt and the second one swdt. The maximum allowed delay between settings of the wdt and swdt is 12 instruction cycles. While this period has expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of the wdtrel register and wdt is automatically reset. The procedure is as "Start procedure" before.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 13
Publication Date: JAN. 2006 Revsion : C
tm
MSB eal
TE CH
T81L0006A/B
! Special Function Registers a) Interrupt Enable 0 register (ien0) The ien0 register (address : A8)
wdt et2 es0 et1 ex1 et0 LSB ex0
The ien0 bit functions
Function Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before swdt is set to ien0.6 wdt prevent an unintentional refresh of the watchdog timer. The wdt is reset by hardware 12 instruction cycles after it has been set. Note: other bits are not used to watchdog control Bit Symbol
b) Interrupt Enable 1 register (ien1) The ien1 register (Address : B8)
MSB swdt pt2 ps pt1 px1 pt0 LSB px0
The ien1 bit functions
Bit Ien1.6 Symbol swdt Function Watchdog timer start refresh flag. Set to active/refresh the watchdog timer. When directly set after setting wdt, a watchdog timer refresh is performed. Bit swdt is reset by hardware 12 instruction cycles after it has been set.
Pay attention that when write ien1.6, it write the swdt bit, when read ien1.6, we will read out the wdts bit. Ie. Watch dog timer status flag. Set by hardware when the watchdog timer was started.
d) Watchdog Timer Reload register (wdtrel)
The wdtrel register ( Address : 86 ) MSB 7 6 5 The wdtrel bit functions Bit Symbol wdtrel.7 wdtrel.6 t0 wdtrel.0 7 6-0 4 3 2 1 LSB 0
Function Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt
The wdtrel register can be loaded and read any time
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 14
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
! WDT Reset
A high on reset pin or watchdog reset request for two clock cycles while the oscillator is running resets the device. Diagram
b) Watchdog timer reset
7FFBH
7FFCH
0000H
Figure Watchdog reset timing **Note : clk: external clock input Tclk: clock period wdt: watchdog timer registers wdts: watchdog timer status flag reset: external reset input rst: internally generated reset signal
!
Reset Time Formula
Reset time=(7FFCh-wdth.wdtl)*presc*48/ClockFrequency while presc=16 if wdtrel.7=1, presc=1 if wdtrel.7=0. For example if you use frequency clock=12MHz, wdtrel=10111111b which means wdtrel.7=1 and wdth=3Fh Then reset time= (7FFCh-3F00h)*48/12M=66544 us
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 15
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
10.4 External Register Table ( for A/D Converter , PWM, EEPROM & LVR)
Register Address (A15...A5-A0) 100... 0010 0000 100... 0010 0001 100... 0010 0010 100... 0010 1010 100... 0010 0101 100... 0010 1011 100... 0010 0110 100... 0010 0111 100... 00101000 100... 0010 1001 100... 0010 1110 100... 0010 1111 100... 0010 1100 100... 0010 1101 100... 0011 0000 100... 0011 0001 100... 0011 0010 Hex 8020H 8021H 8022H 802aH 8025H 802bH 8026H 8027H 8028H 8029H 802eH 802fH 802cH 802dH 8030H 8031H 8032H Name ADM ADR ADB ADE PWMC1 PWMC2 PWM1 PWM2 SPICON OPCODE DATAW_H DATAW_L DATAR_H DATAR_L Port3 HDS Port2 HDS Port1 HDS Comments A/D Control & Status A/D Clock prescaler and A/D value LSB A/D value MSB A/D Converter Channel Enable PWM Control register1 PWM Control register2 and LVR(Low Voltage Reset)* PWM1 Value PWM2 Value EEPROM control & setup (for T81L0006B only) EEPROM opcode (for T81L0006B only) EEPROM write high byte (for T81L0006B only) EEPROM write low byte (for T81L0006B only) EEPROM read high byte (for T81L0006B only) EEPROM read low byte (for T81L0006B only) Port3 I/O high driving set** Port2 I/O high driving set** Port1 I/O high driving set**
Note : * LVR (Low Voltage Reset) address : 802bH, read/write MSB Bit 7 Bit 6 Bit5 Bit 4 LVR[7]
Bit 3 Bit 2 PWM Control register2
Bit1
LSB Bit 0
LVR[7] : if LVR[7] write `1', low voltage reset function enable(under 2.1V reset). default is `0', low voltage reset function disable.
** Port I/O high driving set if write `0' = set I/O to high driving current mode. if write `1' = set I/O to normal driving current mode. default is set `1'. Port 3 high driving address : 8030H MSB Bit 7 Bit 6 Bit5 Port3.7 Port3.6 Port3.5 Port 2 high driving address : 8031H MSB Bit 7 Bit 6 Bit5
Bit 4 Port3.4
Bit 3 Port3.3
Bit 2 Port3.2
Bit1 Port3.1
LSB Bit 0 Port3.0
Bit 4
Bit 3 Port2.3
Bit 2
Bit1 Port2.1
LSB Bit 0 Port2.0
Port 1 high driving address : 8032H MSB Bit 7 Bit 6 Bit5 Port1.7 Port1.6 Port1.5
Bit 4 Port1.4
Bit 3 Port1.3
Bit 2 Port1.2
Bit1 Port1.1
LSB Bit 0 Port1.0
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 16
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
10.5 A/D converter
The data acquisition component is an 8-bit analog-to-digital converter, 8-channel multiplexer and microcontroller compatible control logic. The 8-bit A/D converter uses successive approximation conversion technique. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full-scale adjustments. The design of the component has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The component offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suitable from process and machine control to consumer applications.
A/D Converter Register Control ADM ADR ADB ADE ADENB
Default 00100000 Default x010xxxx Default xxxxxxxx Default 00000000 R/W ADENB R ADB7 R/W ENCH7 R/W ADS R/W ADPS2 R ADB6 R/W ENCH6 R EOC R/W ADPS1 R ADB5 R/W ENCH5 R/W ADI R/W ADPS0 R ADB4 R/W ENCH4 R ADB3 R/W ENCH3 R/W CHS2 R ADB2 R/W ENCH2 R/W CHS1 R ADB1 R/W ENCH1 R/W CHS0 R ADB0 R/W ENCH0
Disable all A/D converter input channels: 0-Disable, 1-Enable If ADENB=0, all input channel will be closed. If ADENB =1, each input channels is individually enabled or disabled by setting or clearing ENCH7~ENCH0 enable bits. ADI A/D Interrupt bit: 0-Disable, 1-Enable If ADI=1, external interrupt 1 will be inhibited. A/D converter interrupt function will in place of external interrupt 1 function. ADS A/D Start bit: 0-Stop, 1-Start EOC A/D Status bit: 0- Busy, 1-End of converting and clear ADS bit CHS2: CHS0 --- Channel select ADPS2: ADPS0 ---A/D clock divider, Input frequency = FOSC/3 ADPS2:1:0 000 001 010 011 100 101 110 111 Dividers Ratio Fad: Fosc/12 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
ADB7 ~ADB0--- 8-bit ADC converting data ENCH7 ~ENCH0 --- ADC individual input channel enable bit: 0-Disable, 1-Enable
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 17
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
A/D converter conversion flow
Set ADENB=1 EOC signal from high go low. (ADC operating) Set ENCH7~ENCH0 (Enable individually channel)
Microcontroller detect EOC signal. rising edge. (ADC conversion complete)
Set CHS[2:0] register bit (Chose ADC input channel) Microcontroller read ADC conversion data from D[7:0] ADC starts conversion (EOC register) bit turn `1'. (ADS register) bit turn `0'.
When set (ADS register )bit=1, and then (EOC register) bit will be turn low.
END Microcontroller generate ADS signal pulse to ADC. 1'ADCLKA/D Converter Timing Diagram
RB ADCLK ADS CHS[2:0] AN[7:0] 16 ADCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
10 ADCLK < TIME < 16 ADCLK
EOC PCHA D[7:0]
5 ADCLK
1.5 ADCLK
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 18
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
10.6 Pulsed Width Modulator (PWM)
The T81L0006A/B provides 2 channels 8 bits PWM output for peripheral. The frequency source of the PWM counter comes from Fosc. Writing 1 to PWMC register enable bit will enable the PWM output function. PWMPS2:1:0 control bit determine PWM output clock that range from Fosc/2 to Fosc/256. Each PWM output clock duty cycle can be programmed though set PWM0 or PWM1 register.
PWM Register Control PWMC1 PWMC2 PWM1 PWM2
Default 0x00 Default 0x00 B7: R/W Pwm2EN R/W 0x00 0x00 B6: R/W Pwm2PS2 R/W B5: R/W Pwm2PS1 R/W B4: R/W Pwm2PS0 R/W B3: R/W Pwm1EN R/W B2: R/W Pwm1PS2 R/W B1: R/W Pwm1PS1 R/W B0: R/W Pwm1PS0 R/W Mode R/W
PWMC1: PWM control register1
Pwm1EN, Pwm2EN PWM1, PWM2 Enable bit: 0-Disable, 1-Enable When Enable bit=0, PWM output pin = High impedance. PWMPS2:1:0 --- PWM dividers ratio Fpwm= Fosc/PWMPS/256 while select 8-bit mode Fpwm= Fosc/PWMPS/65536 while select 16-bit mode PS:2:1:0 000 001 010 011 100 101 110 111 Dividers ratio Fpwm:Fosc 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
PWMC2: PWM control register2 Mode PWM 16-bit mode or 8-bit mode selects : `0'= 8-bit mode, `1'= 16-bit mode When select 16-bit mode, PWM2 register= PWM duty cycle value high byte. PWM1 register= PWM duty cycle value low byte. Note: 16-bit PWM just for PWM1 output
PWM1 register:
Set PWM1's duty cycle. --- Duty1= PWM1/256 or 16-bit PWM duty cycle value low byte.
PWM2 register:
Set PWM2's duty cycle. --- Duty2= PWM2/256 or 16-bit PWM duty cycle value high byte. Set 16-bit PWM duty cycle. --- Duty= (PWM2, PWM1)/65536
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 19
Publication Date: JAN. 2006 Revsion : C
tm
TE CH
T81L0006A/B
10.7 EEPROM Interface (for T81L0006B only)
The EEPROM interface timing is fully compatible with 93C46. To access or send data from/to T81L0006B , 6 registers are going to be controlled. EEPROM Register Control SPICON OPCODE DATAW_H DATAW_L DATAR_H DATAW_L SPICON: MSB Bit 7
Default 00H 00H 00H 00H ----------B2: R/W Epdiv1 B1: R/W Epdiv0 B0: R/W Epst W
Bit 6
Bit5
Bit 4
Bit 3
Bit 2 Epdiv1
Bit1 Epdiv0
LSB Bit 0 Epst
Epst: start EEPROM timing. "1" to start and will be auto cleared after timing finish. Epdiv[1..0]: divide input clock into EEPROM system clock. 10: divide by 64 01: divide by 32 else: divide by 16 OPCODE MSB Bit 7 Bit 6 OP Code
Bit5
Bit 4
Bit 3 address
Bit 2
Bit1
LSB Bit 0
Instruction Set Read WEN (Write Enable) Write WRALL (Write All Registers) WDS (Write Disable) Erase ERAL
OP Code 10 00 01 00 00 11 00
Address A5-A0 11xxxx A5-A0 01xxxx 00xxxx A5-A0 10xxxx
Input Data
D15-D0 D15-D0
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 20
Publication Date: JAN. 2006 Revsion : C
tm
Port1
TE CH
T81L0006A/B
11. I/O Ports
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 output buffers can sink/source four external TTL device inputs. When port 1 pins are written as 1's, these pins are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pull-ups. Port 1 also serves the analog signal input of A/D converter, as listed below: P1.0 ADI0 (analog input signal channel 0) P1.1 ADI1 (analog input signal channel 1) P1.2 ADI2 (analog input signal channel 2) P1.3 ADI3 (analog input signal channel 3) P1.4 ADI4 (analog input signal channel 4) P1.5 ADI5 (analog input signal channel 5) P1.6 ADI6 (analog input signal channel 6) P1.7 ADI7 (analog input signal channel 7)
Port2.0, 2.1, 2.3
Port2.0, 2.1, 2.3 are a bi-directional I/O port with internal pull-ups. Port2.0, 2.1, 2.3 output buffers can sink/source four external TTL device inputs. When Port2.0, 2.1, 2.3 pins are written as 1's, these pins are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port2.0, 2.1, 2.3 pins that are externally being pulled low will source current because of the internal pull-ups. Port 2.0 also serves the output signal of PWM 2.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 output buffers can sink/source four external TTL device inputs. When port 3 pins are written as 1's, these pins are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the internal pull-ups. Port 3 also serves the functions of various special features, as listed below: P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 PWM1 (PWM 1 signal output) P3.7 VREF (external reference voltage input for ADC)
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 21
Publication Date: JAN. 2006 Revsion : C
tm
20
TE CH
T81L0006A/B
Package Dimension
20/24-LEAD SOP
11
H
E
0 .0 1 6 t y p
0 .0 5 0 t y p
D
10
1
A
0 .0 2 0 X 4 5
X
0 .0 0 4 m a x
20-LEAD
SYMBOLS A A1 D E H L X UNIT: INCH MIN. 0.093 0.004 0.496 0.291 0.394 0.016 0 MAX. 0.104 0.012 0.508 0.229 0.419 0.050 8 SYMBOLS A A1 D E H L X
A1
L
24-LEAD
MIN. 0.093 0.004 0.599 0.291 0.394 0.016 0 MAX. 0.104 0.012 0.624 0.229 0.419 0.050 8
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 22
Publication Date: JAN. 2006 Revsion : C
tm
20
TE CH
T81L0006A/B
Package Dimension
20/24-LEAD DIP
D
11
E1
10
1
C
S
A2
L
e1
B B1
20-LEAD
SYMBOLS A A1 A2 B B1 C D E E1 e1 L eA S MIN. 0.015 0.125 0.016 0.058 0.008 1.012 0.290 0.245 0.090 0.120 0.335 NOM 0.130 0.018 0.060 0.010 1.026 0.300 0.250 0.100 0.130 0.355 MAX. 0.175 0.135 0.020 0.064 0.011 1.040 0.310 0.225 0.110 0.140 0.375 0.075 SYMBOLS A A1 A2 B B1 C D E E1 e1 L eA S MIN. 0.015 0.125 0.016 0.058 0.008 1.230 0.290 0.245 0.090 0.120 0.335 -
A1
A
24-LEAD
NOM 0.130 0.018 0.060 0.010 1.250 0.300 0.250 0.100 0.130 0.355 MAX. 0.175 0.135 0.020 0.064 0.011 1.280 0.310 0.225 0.110 0.140 0.375 0.075
UNIT: INCH
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 23
Publication Date: JAN. 2006 Revsion : C
eA
E

▲Up To Search▲

Price & Availability of T81L0006A06

	To Download T81L0006A06 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .